I. Field of the Invention
The present invention relates to a composite semiconductor device and, more particularly, to a composite semiconductor device which consists of a high voltage power element and an integrated circuit formed on one chip and which has a deep element isolation region.
II. Description of the Prior Art
A conventional composite semiconductor device consisting of a high voltage power element and an integrated circuit formed on one chip will be described with reference to FIG. 1.
FIG. 1 is a sectional view showing a semiconductor device in which a power transistor section formed from the upper to lower surface of the semiconductor device and an IC section for controlling the transistor section are formed on one chip. Referring to FIG. 1, n-type epitaxial layer 22 is formed on a p-type semiconductor substrate 21. Epitaxial layer 22 is divided into a power transistor section and a control IC section. Power transistor 30 in the power transistor section comprises n-type base region 25, forming part of epitaxial layer 22, p.sup.+ -type emitter region 24 and n.sup.+ -type base contact region 25a formed in base region 25, and p-type collector layer 21 and p.sup.+ -type collector contact layer 26 constituting the semiconductor substrate. Collector electrode 27 is formed on the bottom surface of the structure.
The control IC section comprises active elements (e.g., bipolar or MOS transistors) and passive elements (e.g., resistors, capacitors, and the like) formed in the epitaxial layer. The number of elements differs depending on the type of device, but in general, several elements are formed. In FIG. 1, p-channel MOS transistor 31 and bipolar transistor 32 are exemplified as active elements.
p.sup.++ -type region 23 isolates the power transistor section from the control IC section and reaches as far as p-type collector layer 21. Epitaxial layer 22, in which the control IC section is formed, is thus surrounded by region 23 and collector layer 21. More specifically, a pn junction is formed around the control IC section. Normally, since collector electrode 27 is fixed at a minimum potential in the substrate, the pn junction is reverse-biased during turn-on of the device, thus forming a depletion layer which performs element isolation.
However, this conventional isolation technique using a pn junction has the following drawbacks.
(a) Since element isolation is performed using a depletion layer formed when the pn junction is reverse-biased, the breakdown voltage is limited to about 300 V. Therefore, when a 1,000 V class high voltage element (e.g., a power transistor) is to be formed, this isolation technique cannot provide a breakdown voltage high enough to form the element together on one chip with a control IC.
(b) Even when a 300 V class power element is to be formed, impurity diffusion must be performed to a depth of 40 .mu.m or more in order to form a pn junction for isolation, a time consuming process. Since the diffusion width along the lateral direction is increased, the size of the element formation region is reduced.
(c) A power element normally generates a large amount of heat, thus increasing the temperature of the pellet. A control IC section formed together on one chip with the power element is directly influenced by increases in temperature, and can easily malfunction.